The present invention relates to a sense amplifier circuit, and more particularly to a sense amplifier circuit for amplifying a current read out from a memory cell for use in a semiconductor memory device and improved in high speed performance of a read out operation.
FIG. 1 is a circuit diagram illustrative of a conventional sense amplifier circuit having an invertor at an output portion. Read bus lines RBT and RBB are connected to digit lines TRUE and BAR respectively. A potential difference is generated based upon read out data from the memory cells in read-out operation and the potential difference is transferred through p-channel MOS field effect transistors P4 and P5 to a sense amplifier SA. A circuit configuration including p-channel MOS field effect transistors P1, P2 and P3 serves as a pre-charge equalizer for pre-charge equalizing the read bus lines RBT and RBB. The above p-channel MOS field effect transistors P4 and P5 connect the lead bus lines RBT and RBB to the sense amplifier SA for transferring the potential difference between the lead bus lines RBT and RBB to the sense amplifier, so as to disconnect the lead bus lines RBT and RBB from the sense amplifier SA at the same time when the sense amplifier SA is activated upon a signal SE2. Further, p-channel MOS field effect transistors P6 and P7 are provided at output portions X2 and X1 respectively of the sense amplifier SA, so that upon receipt of a signal SAEQ, the sense amplifier SA is pre-charged to inactivate the sense amplifier SA.
The sense amplifier SA comprises p-channel MOS field effect transistors P8 and P9 and n-channel MOS field effect transistors N1, N2 and N3. Namely, the sense amplifier circuit is a full-latch sense amplifier which comprises a first invertor comprising the p-channel MOS field effect transistor P8 and the n-channel MOS field effect transistor N1 and a second invertor comprising the p-channel MOS field effect transistor P8 and the n-channel MOS field effect transistor N2. The signal SE1 is inputted into a gate of the n-channel MOS field effect transistor N3. The signal SE2 is inputted into sources of the p-channel MOS field effect transistors P8 and P9. The sense amplifier SA is activated by the signals SE1 and SE2.
Further, invertors I1 and I3 are connected to the output portions X2 and X1 of the sense amplifier SA. The invertor I2 outputs a signal with the same phase as the invertor I3. Output terminals of the invertors I2 and I3 are connected to gates of p-channel MOS field effect transistor P10 and n-channel MOS field effect transistor N4. The p-channel MOS field effect transistor P10 and the n-channel MOS field effect transistor N4 are connected through a connecting point to each other and a WRB line is connected to this connecting point, so that an output signal of high or low "H" or "L" appears on this WRB line.
Prior to the read out operation, the signals SAEQ, SE1 and SE2 are in the low level "L". The signal SAEQ is changed from the low level "L" to the high level "H", so that the p-channel MOS field effect transistors P1-P3, P6 and P7 turn OFF, whereby the potential difference between the read bus lines RBT and RBB becomes transferable to the sense amplifier SA. The word line is then selected to fetch data from the cell connected to the selected word line, whereby the read bus lines RBB and RBT are opened to cause the potential difference to be transferred to the sense amplifier SA. Subsequently, the signal SE1 is changed from the low level "L" to the high level "H", so that the n-channel MOS field effect transistor N3 turns ON. The signal SE2 is then changed from the low level "L" to the high level "H" thereby activating the sense amplifier SA and concurrently the p-channel MOS field effect transistors P4 and PS turn OFF, whereby the read bus lines RBT and RBB become disconnected from the sense amplifier SA. As described above, the sense amplifier SA comprises the first invertor circuit and the second invertor circuit. The activated sense amplifier SA amplifiers data on the read bus lines RBT and RBB to define the data, whereby the output from the sense amplifier SA is transferred through the invertors I1, I2 and I3 to the p-channel MOS field effect transistor P10 and the n-channel MOS field effect transistor N4, so that a high "H" or low "L" output appears on the WRB.
In the above conventional sense amplifier circuit, the invertors I1, I2 and I3 are provided between the read bus lines RBT and RBB and the output transistors P10 and N4, for which reason those invertors cause signal transmission delays, thereby making it difficult to improve the high sped performance of the sense amplifier circuit. In order to reduce the signal transmission delay, it is effective to enlarge the size of the invertor circuits. This enlargement in size of the invertor circuits, however, causes an enlargement in occupied area of the invertor circuits, thereby making it difficult to satisfy the requirements for scaling down of the sense amplifier circuit as well as for increase the density of integration of the sense amplifier circuit. The individual invertors also serve as loads to the read bus lines RBT and RBB, whereby the output signals are delayed, thereby making it difficult to improve the high speed performance of the sense amplifier circuit.
In the above circumstances, it had been required to develop a novel sense amplifier Circuit free from the above problems.